Flip-chip ball grid array (FCBGA) semiconductor package relates to a combination of flip chip and ball grid array, which allows an active surface of at least one chip mounted therein to be electrically connected to a surface of a substrate via a plurality of solder bumps, and a plurality of solder balls to be implanted on another surface of the substrate, wherein the solder balls serve as input/output (I/O) connections for the semiconductor package. This semiconductor package yields significant advantages to effectively decrease the package size, reduce resistance and improve electrical performances to prevent decay of signals during transmission without using conventional bonding wires. Therefore, the FCBGA semiconductor package is considered providing a major packaging technology for chips and electronic elements of the next generation.
As shown in FIG. 10, a FCBGA semiconductor package comprises a substrate 70; a chip 71 mounted on and electrically connected to an upper surface of the substrate 70 in a flip-chip manner; and a plurality of solder balls 72 implanted on a lower surface of the substrate 70, for electrical connection with an external device. The semiconductor package further comprises an encapsulant 73 formed on the upper surface of the substrate 70 by a molding process for encapsulating the chip 71. Related prior arts include U.S. Pat. Nos. 6,038,136, 6,444,498, 6,699,731 and 6,830,957, which have disclosed similar package structures to improve the electrical performances of packages and satisfy the requirements for advanced electronic products.
U.S. Pat. No. 6,830,957 uses a method to increase the length and width of the substrate 70 for fabricating the semiconductor package. As shown in FIG. 11, the substrate 70 is received in a substrate carrier 75, and a clamping area a is provided as an extension from each side of the substrate 70 to make the substrate 70 larger in size than a mold cavity 81 of an encapsulating mold 80. Thereby, the substrate 70 can be well clamped by the mold 80, and the encapsulant 73 would not flash to the lower surface of the substrate 70 to damage the bondability of ball pads 74 on the substrate 70 where the solder balls 72 are to be implanted. For a single package conventionally having the substrate 70 sized 31 mm×31 mm (as shown in FIG. 10), the clamping area a must be at least 0.6 mm in width to provide a good flash-preventing effect. Accordingly, a portion of at least 1.2 mm that is to be eventually cut off is added respectively to the length and width of the substrate 70, making the material required for the substrate 70 and overall fabrication costs of the package undesirably increased (the substrate cost is generally more than 60% of the overall costs of the flip-chip package).
The cost associated with the substrate 70 is actually more than that described above as compared to the singulated package product shown in FIG. 10. This is because as shown in FIG. 12, a mold-releasing angle 82 must be formed at an edge of the encapsulant 73 in contact with the substrate 70 according to the shape of the mold cavity 81 in order to successfully release the mold 80 after the molding process is complete. Generally, the mold-releasing angle 82 should not be larger than 60° to provide a satisfactory mold-releasing effect. Accordingly, for a single package with the substrate 70 having the size of 31 mm×31 mm, an additional portion b of at least 0.58 mm corresponding to the mold-releasing angle 82 of the encapsulant 73 is required and formed as an extension from each side of the substrate 70. In other words, a portion of 1.16 mm that is to be eventually cut off is added respectively to the length and width of the substrate 70. Further, a cutting path c of 0.3 mm at each side of the substrate 70 is reserved for a singulation process, which leads to an addition of 0.6 mm respectively in the length and width of the substrate 70. Therefore, to have a final package with the substrate 70 of a size of 31 mm×31 mm, the substrate 70 during fabrication of the package must be sized (31+1.2+1.16+0.6) mm×(31+1.2+1.16+0.6) mm in length and width. The increase of substrate size not only causes a waste of substrate utilization but also makes the overall costs increased by about 15 to 20%.
The foregoing drawback leads to significant difficulty in fabrication of the BGA semiconductor package. The molding process for forming the encapsulant 73 is an essential step in the package fabrication, however it makes the size and material cost of the substrate 70 increased, thereby not advantageous for mass production.
Therefore, the problem to be solved here is to provide a method for fabricating semiconductor packages, which can reduce the size and cost of a substrate, prevent resin flashes, and overcome mold-releasing difficulty, to be in favor of mass production.